Title :
On the design of robust multiple fault testable CMOS combinational logic circuits
Author :
Kundu, Sandip ; Reddy, Sudhakar M. ; Jha, Niraj K.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. An integrated approach to the design of combinational logic circuits in which all single stuck-open faults and path delay faults are detectable by robust tests was presented by the authors earlier. It is shown that the earlier design actually results in circuits in which all multiple stuck-at and stuck-open and multipath delay faults are robustly testable. The tests to detect such faults are presented.<>
Keywords :
CMOS integrated circuits; combinatorial circuits; logic design; logic testing; integrated approach; modeled faults; path delay faults; robust multiple fault testable CMOS combinational logic circuits; robust tests; stuck-open faults; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Delay effects; Electrical fault detection; Logic testing; Robustness; Semiconductor device modeling; Timing;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122502
