A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity

Author

Chawla, Ravi ; Bandyopadhyay, Abhishek ; Srinivasan, Venkatesh ; Hasler, Paul

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

651

Lastpage

654

Abstract

We present a 128×32 four-quadrant programmable current-mode analog vector-matrix multiplier (VMM). The proposed multiplier cell operates on a 3.3 V supply, consumes 531 nW/MHz and is linear over two decades of current range. Programmability and non-volatile weight storage is obtained by using floating-gate transistors. Experimental results for a full image discrete cosine transform (DCT) using the proposed architecture is presented. The IC prototype was fabricated in a 0.5 μm CMOS process and occupies 0.83 mm² of area.

Keywords

CMOS analogue integrated circuits; analogue multipliers; current-mode circuits; discrete cosine transforms; linearisation techniques; matrix multiplication; programmable circuits; vectors; 0.5 micron; 3.3 V; CMOS; VMM; current-mode multiplier; discrete cosine transform; floating-gate transistors; four-quadrant multiplier; image DCT; linear vector-matrix multiplier; nonvolatile weight storage; programmable analog multiplier; Analog computers; CMOS integrated circuits; CMOS process; Discrete cosine transforms; Discrete transforms; Linearity; MOSFETs; Prototypes; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358910

Filename

1358910