Title :
A covariance model for the yield of large memory chips
Author :
Stapper, C.H. ; Retersdorf, M.A. ; Rosner, L.G.
Author_Institution :
IBM Technol. Products, Essex Junction, VT, USA
Abstract :
Data from 4-Mb and 16-Mb memory chips show that a new method is required to predict the yield of very large memory chips with redundant word and bit lines. A model developed to do this indicates that gigabit memory chips, with a yield of less than 90%, may be less productive than 256-Mb "cut-down" chips.<>
Keywords :
VLSI; integrated memory circuits; probability; redundancy; semiconductor device models; statistical analysis; chip yield; covariance model; large memory chips; model; redundant bit lines; redundant word lines; Probability; Redundancy; Semiconductor device modeling; Semiconductor memories; Statistics; Very-large-scale integration;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307339
