DocumentCode :
1952063
Title :
Power-aware pipelining design of an 8-bit CLA using PLA-styled all-N-transistor logic
Author :
Wang, Chua-Chin ; Lee, Ching-Li ; Liu, Pai-Li
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fYear :
2004
fDate :
20-23 June 2004
Firstpage :
149
Lastpage :
152
Abstract :
A high speed and low-power 8-bit carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks, which are arranged in a PLA design style with power-aware pipelining is present. The pull-up charging and pull-down dis-charging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. The analysis of the area (transistor count) tradeoff is also presented in this paper. The output of the addition of two 8-bit binary numbers is done in 2 cycles. The proposed power-aware pipelining design methodology takes advantage of shutting down the processing stages with identical inputs in two consecutive cycles. Not only is it proved to be also suitable for the long adders, the power consumption is drastically reduced by at most 50% at every process corner.
Keywords :
MOSFET; adders; carry logic; logic design; low-power electronics; pipeline processing; power consumption; programmable logic arrays; NMOS blocks; PLA design; PLA styled all N-transistor logic; feedback MOS transistors; high speed carry lookahead adder; low power carry lookahead adder; power aware pipelining design; power consumption; Adders; CMOS logic circuits; Clocks; Energy consumption; Logic arrays; Logic design; MOSFETs; Output feedback; Pipeline processing; Programmable logic arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN :
0-7803-8322-2
Type :
conf
DOI :
10.1109/NEWCAS.2004.1359044
Filename :
1359044
Link To Document :
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