DocumentCode :
1952621
Title :
Design constraints of a hypertransport-compatible network-on-chip
Author :
Hasan, Syed Kafay ; Landry, Alexandre ; Savaria, Yvon ; Nekili, Mohained
Author_Institution :
Concordia Univ., Montreal, Que., Canada
fYear :
2004
fDate :
20-23 June 2004
Firstpage :
269
Lastpage :
272
Abstract :
Hypertransport (HT) is an emerging system integration communication technology. There is a need for a network on chip (NOC) technology compatible with this cutting-edge system technology. This paper reveals design constraints involved in implementing an HT-compatible NOC. In order to provide a simple and HT-compatible solution, we propose an architecture called hypertransport super lite (HTSL). The new architecture allows a reduction of more than 14 times in required buffer space, while keeping the functionality unaffected. Moreover, exploiting the advantages of on-chip architecture leverages the processing complexity of each node in the architecture.
Keywords :
integrated circuit design; parallel architectures; system-on-chip; cutting edge system technology; hypertransport compatible network-on-chip; hypertransport super lite; network on chip architecture; Communication industry; Communication standards; Communications technology; Frequency; Microprocessors; Modems; Network-on-a-chip; Scalability; Space technology; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN :
0-7803-8322-2
Type :
conf
DOI :
10.1109/NEWCAS.2004.1359083
Filename :
1359083
Link To Document :
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