Three dimensional analysis of thermal degradation effects in FDSOI MOSFETs

Fully Depleted Silicon-on-Insulator (SOI) devices have led to better electrical characteristics (e.g., reduced junction depth, increased channel mobility, suppressed short channel effect, excellent latchup immunity, and improved subthreshold characteristics) than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO₂ layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three dimensional (3D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller than a critical value in a finger-type layout. The current degradation for the 3D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed