VLSI implementation of a wide band, high dynamic range digital drop receiver

The authors discuss the VLSI implementation of a wideband high-dynamic-range digital drop receiver (DDR) in a three-chip set. The chip set is composed of one numerically controlled oscillator/modulator (NCOM) followed by two decimating digital filters (DDFs). A 16 bit real or 32 bit complex sampled data sequence is input into the NCOM at up to 33 megasamples per second. The NCOM performs a tunable complex down-conversion with greater than 90 dB of spurious-free dynamic range and 0.007 Hz accuracy. The real and imaginary output of the NCOM are each sent to a DDF where they are low-pass-filtered with a stop-band attenuation of up to 120 dB and decimated by up to a factor of 16384. The filter characteristics are fully programmable