A novel erasing technology for 3.3 V flash memory with 64 Mb capacity and beyond

A novel erasing scheme has been developed to suppress the distribution of the erased cell threshold voltage (erased-V). The new 2-step erasing scheme consists of two steps of the cell gate bias conditions, that is to apply 1) negative high voltage on the control gate to erase the cell data, and successive 2) positive high voltage to inject a few electrons from the substrate back to the floating gate. The suppressing effect of the erased-V distribution was also confirmed using a 16 Kbit flash memory cell array, the erased-V/sub /distribution drastically decreases from 2.0 V by the conventional erasing scheme to 0.9 V using the 2-step erasing scheme.<>