Title :
Compaction of ATPG-generated test sequences for sequential circuits
Author :
Roy, R.K. ; Niermann, T.M. ; Patel, J.H. ; Abraham, J.A. ; Saleh, R.A.
Author_Institution :
Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
Currently available automatic test pattern generators (ATPGs) generate test sets that are nonoptimal in length. The authors describe novel heuristic techniques to reduce the length of the test set for a sequential circuit by compaction of the automatically generated patterns. Based on these techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry.<>
Keywords :
automatic testing; circuit analysis computing; heuristic programming; integrated circuit testing; integrated logic circuits; sequential circuits; C program; automatic test pattern generators; heuristic techniques; sequential circuits; test sequence compaction; test set length reduction; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Compaction; Costs; Fault detection; Sequential analysis; Sequential circuits; System testing;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122533
