Steady state and pulsed bias stress induced degradation in amorphous silicon thin film transistors for active-matrix liquid crystal displays

The threshold voltage instabilities in nitride/oxide dual gate dielectric hydrogenated amorphous silicon (a-Si:H) thin-film transistors are investigated as a function of stress time, stress temperature and stress bias. The obtained results are explained with a multiple trapping model, rather than weak bond breaking model. In our model, the injected carriers from the a-Si:H channel first thermalize in a broad distribution of localized band-tail states located at the a-Si:H/a-SiN/sub x/:H interface and in the a-SiN/sub x/:H transitional layer close to the interface, then move to deeper energies in amorphous silicon nitride at longer stress times, larger stress electric fields, or higher stress temperatures. The results of the model are consistent with the bias-stress-temperature data. Steady state (DC) as well as pulsed bias stress measurements have been employed to electrically characterize the instabilities in a-Si:H TFTs.<>