Title :
A complementary gain cell technology for sub-1 V supply DRAMs
Author :
Shukuri, S. ; Kure, T. ; Nishida, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A Complementary Gain (CG) cell concept is proposed and experimentally demonstrated to overcome the scaling limit of the conventional DRAM cell. The CG cell performance is described in comparison with a conventional cell from the viewpoint of factors relevant to gigabit integration, such as supply voltage scalability, minimum storage capacitance, immunity to noise on bitline and cell size. The test CG memory cell operation is successfully demonstrated at a supply voltage below 1V.<>
Keywords :
DRAM chips; cellular arrays; memory architecture; 0.9 V; CG cell performance; DRAMs; bitline noise immunity; cell size; complementary gain cell technology; gigabit integration; minimum storage capacitance; scaling limit; supply voltage scalability; Cellular logic arrays; DRAM chips; Memory architecture;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307530
