DocumentCode :
1956169
Title :
ASIC Clock Tree Estimation in Design Planning
Author :
Ang Boon Chong
Author_Institution :
Design Service, PMC-Sierra, Bayan Baru, Malaysia
fYear :
2013
fDate :
29-31 Jan. 2013
Firstpage :
619
Lastpage :
626
Abstract :
In the early ASIC design planning phase, clock tree estimation always based on best guess of the ASIC planner. The critical elements such as power, latency and uncommon buffer in synthesized clock network will affect the performance as well as power definition of ASIC full chip specifications. The intend of this paper is to understand the relationship in terms of clock network latency, clock skew, and clock network power with respect to registers count, floor planning aspect ratio, design utilization and clock tree synthesis constraint. Hopefully the finding will benefit the ASIC planner in reducing the power and timing specification guard band due to the clock network.
Keywords :
application specific integrated circuits; circuit layout; ASIC clock tree estimation; ASIC design planning phase; ASIC full chip specification; clock network latency; clock network power; clock skew; clock tree synthesis constraint; design utilization; floor planning aspect ratio; registers count; synthesized clock network; Application specific integrated circuits; Clocks; Estimation; IP networks; Inverters; Planning; Registers; ASIC Floorplanning; Clock Tree Estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Systems Modelling & Simulation (ISMS), 2013 4th International Conference on
Conference_Location :
Bangkok
ISSN :
2166-0662
Print_ISBN :
978-1-4673-5653-4
Type :
conf
DOI :
10.1109/ISMS.2013.25
Filename :
6498346
Link To Document :
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