iProbe-d: a hot-carrier and oxide reliability simulator

Author

Li, Ping-Chung ; Stamoulis, Georgios I. ; Hajj, Ibrahim N.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1994

fDate

11-14 April 1994

Firstpage

274

Lastpage

279

Abstract

In this paper we describe a hot-carrier and oxide reliability simulator, iProbe-d. In this program, a probabilistic timing approach is employed to find the most susceptible devices to hot-carrier degradation and/or oxide breakdown in a CMOS VLSI digital circuit design under expected operating conditions. After the damage in each device is determined, a combination of damaged-transistor model, RC delay and critical path analysis is used to estimate the impact of hot-carrier effects (HCE) on circuit performance; namely, the increase of circuit delay. The results can then be used to improve the reliability of the circuit prior to fabrication.<>

Keywords

CMOS integrated circuits; VLSI; circuit analysis computing; circuit reliability; delays; dielectric thin films; digital integrated circuits; digital simulation; electric breakdown of solids; electronic engineering computing; hot carriers; semiconductor device models; CMOS VLSI digital circuit design; RC delay analysis; circuit delay; circuit performance; critical path analysis; damaged-transistor model; hot-carrier degradation; hot-carrier reliability simulator; iProbe-d; oxide breakdown; oxide reliability simulator; probabilistic timing method; CMOS digital integrated circuits; Circuit simulation; Degradation; Delay effects; Delay estimation; Digital circuits; Electric breakdown; Hot carriers; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 1994. 32nd Annual Proceedings., IEEE International

Conference_Location

San Jose, CA, USA

Print_ISBN

0-7803-1357-7

Type

conf

DOI

10.1109/RELPHY.1994.307824

Filename

307824