Title :
PLA optimization using output encoding
Author :
Saldanha, A. ; Katz, R.H.
Author_Institution :
Electr. Eng. & Comput. Sci. Dept., California Univ., Berkeley, CA, USA
Abstract :
An automatic tool that heuristically determines a good partitioning of a single large programmable logic array (PLA) into a PLA with a smaller number of encoded outputs (and usually fewer product terms), followed by a set of decoders to regenerate the original outputs, has been developed. Initial results using logic descriptions of processor chips and a benchmark set of industrial PLAs show area savings of up to 35% and delay reductions of up to 45%. The approach can be considered an alternative to Boolean decomposition and factoring in multilevel logic synthesis.<>
Keywords :
VLSI; circuit layout CAD; delays; encoding; logic CAD; logic arrays; Boolean decomposition; PLA optimization; delay reductions; large programmable logic array; multilevel logic synthesis; output encoding; Decoding; Delay; Encoding; Logic arrays; Programmable logic arrays; Rails;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122553
