DocumentCode
1958950
Title
REDI: an efficient fault oriented procedure to identify redundant faults in combinational logic circuits
Author
Chen Wang ; Pomeranz, I. ; Reddy, S.M.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
2001
fDate
4-8 Nov. 2001
Firstpage
370
Lastpage
374
Abstract
In this work, a new and effective procedure, called REDI, to efficiently identify redundant single stuck-at faults in combinational logic circuits is proposed. The method is fault oriented and uses sensitizability of partial paths to determine redundant faults. It uses only implications and hence may not determine all the redundant faults of a circuit. However, experimental results presented on benchmark circuits show that the procedure identifies nearly all the redundant faults in most of the benchmark circuits. The key features of REDI that make it efficient are: partial path sensitization, blockage learning, dynamic branch ordering and fault grouping. Experimental results on benchmark circuits demonstrate the efficiency of the proposed procedure in identifying redundant faults in combinational logic circuits.
Keywords
combinational circuits; fault diagnosis; logic testing; redundancy; REDI; blockage leaming; combinational logic circuit; dynamic branch ordering; fault grouping; fault oriented procedure; partial path sensitization; redundant fault identification; stuck-at fault; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Fault diagnosis; Logic circuits; Logic testing; Optimization methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-7247-6
Type
conf
DOI
10.1109/ICCAD.2001.968649
Filename
968649
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