Title :
Buried gate SOI LIGBT without latch-up susceptibility
Author :
Park, I.-Y. ; Kim, S.-H. ; Choi, Y.-I.
Author_Institution :
Sch. of Electron. Eng., Ajou Univ., Suwon, South Korea
Abstract :
Summary form only given. LIGBT (lateral insulated gate bipolar transistor) is a promising device for smart power ICs due to its low forward voltage drop and high input impedance. Also, the SOI structure has several advantages, such as ease of isolation and low leakage currents. However, the LIGBT contains an inherent parasitic thyristor, which turns on when the voltage drop in the p/sup -/ base layer under the n/sup +/ cathode is above 0.7 V. These phenomenon is called latch-up. The FBSOA (forward biased safe operating area) of the LIGBT is limited by this latch-up phenomenon. In order to prevent latch-up, it is important to reduce the voltage drop due to hole currents. In this paper, a thin film SOI LIGBT with buried gate is proposed to suppress latch-up and is verified by numerical simulation. The buried gate and buried oxide are formed by the reverse silicon wafer direct bonding technique (Matsumoto, IEDM Tech. Dig., pp. 949-51, 1996). Also, in order to reduce the voltage drop due to the p/sup -/ base region, a p/sup +/ region is formed. This enables the proposed LIGBT with buried gate to suppress the parasitic thyristor latch-up and enlarge the FBSOA efficiently.
Keywords :
buried layers; insulated gate bipolar transistors; numerical analysis; power bipolar transistors; power integrated circuits; semiconductor device models; semiconductor device reliability; silicon-on-insulator; FBSOA; LIGBT; SOI structure; Si-SiO/sub 2/; base layer; buried gate; buried gate SOI LIGBT; buried oxide; forward biased safe operating area; forward voltage drop; hole currents; input impedance; isolation; latch-up; latch-up phenomenon; latch-up suppression; latch-up susceptibility; lateral insulated gate bipolar transistor; leakage currents; numerical simulation; parasitic thyristor; parasitic thyristor latch-up; reverse silicon wafer direct bonding technique; smart power ICs; thin film SOI LIGBT; voltage drop; Cathodes; Impedance; Insulated gate bipolar transistors; Leakage current; Low voltage; Numerical simulation; Power integrated circuits; Silicon on insulator technology; Thyristors; Wafer bonding;
Conference_Titel :
SOI Conference, 1998. Proceedings., 1998 IEEE International
Conference_Location :
Stuart, FL, USA
Print_ISBN :
0-7803-4500-2
DOI :
10.1109/SOI.1998.723109
