Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells

It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90 nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the peicewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9 dB (without calibration) is achieved at 210 MSPS from the Verilog synthesized design.