Title :
Power sequence free 400Mbps 90µW 6000µm2 1.8V–3.3V stress tolerant I/O buffer in 28nm CMOS
Author :
Kumar, Vipin ; Rizvi, M.
Author_Institution :
Technol. R&D, STMicroelectron. Pvt. Ltd., Noida, India
Abstract :
A power sequence independent I/O (Input/Output) buffer architecture for high voltage (up to 3.6V) application by using low voltage (1.8V) devices is proposed. In this a power sequence free, area and power efficient CRVG (Configurable Reference Voltage Generator) generates the internal reference voltage for the stacked devices to protect them from voltage stress. The proposed I/O buffer is designed in 28nm CMOS process by using standard 32Å gate-oxide devices. The silicon results confirmed up to 200 MHz successful operation in multiple (1.8V, 2.5V, 3.0V, 3.3V) supply range.
Keywords :
CMOS integrated circuits; buffer circuits; low-power electronics; reference circuits; CMOS process; CRVG; bit rate 400 Mbit/s; configurable reference voltage generator; gate-oxide devices; low voltage devices; power 90 muW; power sequence independent I/O buffer architecture; size 28 nm; voltage 1.8 V to 3.3 V; Computer architecture; Layout; Logic gates; Power demand; Silicon; Stress; Transistors;
Conference_Titel :
ESSCIRC (ESSCIRC), 2013 Proceedings of the
Conference_Location :
Bucharest
Print_ISBN :
978-1-4799-0643-7
DOI :
10.1109/ESSCIRC.2013.6649066
