Title :
An 8-bit 450-MS/s single-bit/cycle SAR ADC in 65-nm CMOS
Author :
Tripathi, Vaibhav ; Murmann, Boris
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
A low-energy 8-bit 450-MS/s single-bit/cycle SAR ADC is presented. The design combines top-plate sampling, small unit capacitances (0.75 fF), symmetric DAC switching, and judicious delay optimization around a single high-speed comparator to achieve an ENOB of 7.6 at Nyquist, translating into an FOM of 76 fJ/conversion-step. The converter occupies an active area of 0.035 mm2 in 65-nm CMOS.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; comparators (circuits); CMOS; ENOB; FOM; SAR ADC; capacitance 0.75 fF; delay optimization; single high-speed comparator; size 65 nm; symmetric DAC switching; top-plate sampling; word length 8 bit; CMOS integrated circuits; Capacitance; Clocks; Delays; Latches; Optimization; Switches;
Conference_Titel :
ESSCIRC (ESSCIRC), 2013 Proceedings of the
Conference_Location :
Bucharest
Print_ISBN :
978-1-4799-0643-7
DOI :
10.1109/ESSCIRC.2013.6649086
