• DocumentCode
    1962042
  • Title

    A 9b 2GS/s 45mW 2X-interleaved ADC

  • Author

    Pernillo, Jorge ; Flynn, Michael P.

  • Author_Institution
    Dept. of EECS, Univ. of Michigan, Ann Arbor, MI, USA
  • fYear
    2013
  • fDate
    16-20 Sept. 2013
  • Firstpage
    125
  • Lastpage
    128
  • Abstract
    A 9b 2GS/s ADC architecture interleaves a pair of two-stage pipeline ADCs to achieve high performance with a shared low-gain op-amp and a shared low-accuracy 2nd stage sub-ADC. This technique reduces area and eliminates the need to correct for gain and offset mismatch between channels. The ADC achieves a measured ENOB of 7.07b for a 1GHz signal input sampled at 2GS/s and consumes 45mW from a 1.0V supply, yielding an FOM of 167fJ/conversion-step.
  • Keywords
    analogue-digital conversion; operational amplifiers; 2X-interleaved ADC architecture; FOM; figure of merit; frequency 1 GHz; offset mismatch; power 45 mW; shared low-accuracy 2nd stage subADC; shared low-gain op-amp; voltage 1.0 V; word length 9 bit; CMOS integrated circuits; CMOS technology; Calibration; Capacitors; Clocks; Delays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ESSCIRC (ESSCIRC), 2013 Proceedings of the
  • Conference_Location
    Bucharest
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4799-0643-7
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2013.6649088
  • Filename
    6649088
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1962042