A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS

A 6-bits 6-GS/s flash ADC is presented. Single-stage integrators are proposed as preamplifiers to drive the comparators. Compared to single-stage voltage amplifiers, integrators limit the gain-bandwidth requirements leading to lower power dissipation and smaller device size. Comparators are interleaved and clocked at half rate, limiting dissipation thanks to the longer available regeneration time. Offsets of the front-end are continuously calibrated in background. The ADC, realized in a 32nm Low Power CMOS technology proves a very robust operation with SNDR degradation of only 1.5dB going from 1GS/s to 6GS/s. ENOB at 6GS/s with Nyquist frequency input is 5.25 with power dissipation of 95mW from 1V supply. The corresponding FoM is 416fJ/conv. To the Authors knowledge the converter displays also the highest speed among CMOS flash ADCs with more than 4 effective bits of resolution.