DocumentCode
1962350
Title
A streamlined DSP microprocessor architecture
Author
Takefman, Michael ; Chow, Paul
fYear
1991
fDate
14-17 Apr 1991
Firstpage
1257
Abstract
A microprocessor architecture for digital signal processing is described. The architecture offers almost twice the performance of the Motorola DSP56000 microprocessor, while maintaining assembly-code compatibility. Improved performance is achieved by streamlining the instruction set, using a seven-stage pipeline, and adding a second memory write stage late in the pipeline
Keywords
digital signal processing chips; pipeline processing; reduced instruction set computing; RISC; digital signal processing; microprocessor architecture; reduced instruction set computer; second memory write stage; seven-stage pipeline; streamlined DSP microprocessor; Adaptive filters; Assembly; Clocks; Computer architecture; Digital signal processing; Finite impulse response filter; IIR filters; Microprocessors; Pipelines; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on
Conference_Location
Toronto, Ont.
ISSN
1520-6149
Print_ISBN
0-7803-0003-3
Type
conf
DOI
10.1109/ICASSP.1991.150624
Filename
150624
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