DocumentCode :
1962387
Title :
Design Methodology for Clocked Storage Elements Robust to Process Variations
Author :
Moon, Joosik ; Aktan, Mustafa ; Oklobdzija, Vojin G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at Dallas, Richardson, TX, USA
fYear :
2009
fDate :
11-16 Oct. 2009
Firstpage :
20
Lastpage :
23
Abstract :
In this paper we address the effects of process variations on the performance of clocked storage elements. Two types of structures are selected and evaluated by using energy-delay space analysis. The delay variations of the energy-efficient designs for each clocked storage element are measured and compared. We show how much topology selection is important in order to minimize the impact of process variations on performance and reliability.
Keywords :
CMOS digital integrated circuits; clocks; delays; flip-flops; integrated circuit design; integrated circuit reliability; semiconductor storage; CMOS technology; clocked storage element design methodology; dynamic flip-flop; energy-delay space analysis; energy-efficient design; process variations; reliability; robustness; static latch; topology selection; CMOS technology; Clocks; Delay; Design methodology; Energy consumption; Energy efficiency; Integrated circuit technology; Robustness; Space technology; Topology; Clocked storage elements; Process variations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advances in Circuits, Electronics and Micro-electronics, 2009. CENICS '09. Second International Conference on
Conference_Location :
Sliema
Print_ISBN :
978-0-7695-3832-7
Type :
conf
DOI :
10.1109/CENICS.2009.16
Filename :
5291509
Link To Document :
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