A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply

Author

Yao Liu ; Bonizzoni, Edoardo ; D´Amato, Alessandro ; Maloberti, Franco

Author_Institution

Dipt. di Ing. Ind. e dell´Inf., Univ. of Pavia, Pavia, Italy

fYear

2013

fDate

16-20 Sept. 2013

Firstpage

371

Lastpage

374

Abstract

This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements. The circuit, fabricated in a mixed 0.18-0.5-μm CMOS technology, achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods. A single-step chopping of the input stage leads to a residual offset of 9.7 μV. The measured SFDR and power consumption are -90 dB and 280 μW, respectively. The achieved Figure of Merit is 177.5 dB.

Keywords

CMOS integrated circuits; digital-analogue conversion; bandwidth 5 kHz; dynamic elemnent matching; mismatch compensation; mixed CMOS technology; multilevel DAC unity elements; multilevel second-order incremental converter; power 280 muW; single-step chopping; size 0.18 mum to 0.5 mum; smart-DEM algorithm; voltage 3.3 V; word length 3 bit; Adders; Bandwidth; Clocks; Finite element analysis; Histograms; Modulation; Power measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2013 Proceedings of the

Conference_Location

Bucharest

ISSN

1930-8833

Print_ISBN

978-1-4799-0643-7

Type

conf

DOI

10.1109/ESSCIRC.2013.6649150

Filename

6649150