Title :
Mind: a module binder for high level synthesis
Author :
Tseng, Chia-Jeng ; Rothweiler, Steven G. ; Sutarwala, Shailesh ; Prabhu, Ajit M.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
Mind, a module binder for the Bridge synthesis system, is described. The practical considerations for generating production-quality designs are emphasized. These considerations include the separation of single-function and multiple-function ALU (arithmetic and logic unit) generators, the extraction of constant and feedthrough control signals, as well as the incorporation of a net-list post processor to eliminate constant inputs, floating outputs, and feedthrough wires. Experimental data indicate that the application of these optimization techniques results in significant area reduction
Keywords :
circuit layout CAD; Bridge synthesis system; Mind; area reduction; arithmetic and logic unit; constant control signals; constant inputs; feedthrough control signals; feedthrough wires; floating outputs; high level synthesis; module binder; multiple-function generators; net-list post processor; optimization techniques; production-quality designs; signals extraction; single-function ALU generators; Arithmetic; Bridges; Control system synthesis; Data mining; High level synthesis; Logic; Signal generators; Signal processing; Signal synthesis; Wires;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63400