Title :
A throughput-agnostic 11.9–13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS
Author :
Fang-Li Yuan ; Palani, Rakesh Kumar ; Basir-Kazeruni, Sina ; Shih, Hundo ; Saha, Anindya ; Harjani, Ramesh ; Markovic, Dejan
Author_Institution :
Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
A blind classification SoC for cognitive radios, featuring multi-signal channelization, 16-core dynamic parallelism-frequency scaling and GALS-based multithreading, is realized in 40nm CMOS. Targeting ≥95% detection probability and <; 0.5% false-alarm rate, the SoC achieves a throughput-insensitive energy efficiency of 11.9-13.6GOPS/mW for multiple 7.8-125MHz bandwidth-agnostic signals in a 500MHz channel. The SoC shows 2.1× lower energy, >2.7× less efficiency variation, 1.2× baseband area and up to 4× processing time reduction compared to prior work. Throughput-matched scheduling of spatial resources enables operation at peak energy efficiency without the need for any voltage adjustment.
Keywords :
CMOS integrated circuits; cognitive radio; multi-threading; scheduling; signal classification; system-on-chip; 16-core dynamic parallelism-frequency scaling; CMOS; GALS-based multithreading; bandwidth-agnostic signals; blind classification SoC; cognitive radios; detection probability; false-alarm rate; frequency 500 MHz; frequency 7.8 MHz to 125 MHz; multisignal channelization; peak energy efficiency; size 40 nm; spatial resources; throughput-insensitive energy efficiency; throughput-matched scheduling; Energy efficiency; Parallel processing; Reduced instruction set computing; Synchronization; System-on-chip; Throughput;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231245
