A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs

Author

Pei-Wen Luo ; Chi-Kang Chen ; Yu-Hui Sung ; Wei Wu ; Hsiu-Chuan Shih ; Chia-Hsin Lee ; Kuo-Hua Lee ; Ming-Wei Li ; Mei-Chiang Lung ; Chun-Nan Lu ; Yung-Fa Chou ; Po-Lin Shih ; Chung-Hu Ke ; Chun Shiah ; Stolt, Patrick ; Tomishima, Shigeki ; Ding-Ming Kwai

Author_Institution

ITRI, Hsinchu, Taiwan

fYear

2015

fDate

17-19 June 2015

Abstract

Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and <;10ns read latency on a 45nm DRAM process. The architecture is based on small subarrays with short WL and BL to realize the low latency and energy efficiency. We also integrated several circuit techniques, including adaptive power to speed-up access time and banks rotation to reduce thermal issues. The proposed device is also estimated in a system simulation that shows that the power efficiency is higher than comparable systems.

Keywords

DRAM chips; circuit CAD; three-dimensional integrated circuits; 16 channel DRAM; 3D stacked memory device; TSV; computer-aided design methodology; dynamic random-access memory; energy efficiency; size 45 nm; thermal issue reduction; through silicon via; Arrays; Bandwidth; Energy efficiency; Performance evaluation; Random access memory; Three-dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSI Circuits), 2015 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-86348-502-0

Type

conf

DOI

10.1109/VLSIC.2015.7231256

Filename

7231256