A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΔΣ ADC with a FoM of 1pJ/bit in 130nm CMOS

A 4^th order RF LC ΔΣ ADC clocked at 3.6GHz and centered at 900MHz is presented. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. The ADC, suitable for Software Defined Radio applications, is implemented in a standard 130nm CMOS technology. It achieves a 52dB SFDR and a 50dB SNDR in a 28MHz BW and consumes only 15mW from a 1.2V supply. The Figure of Merit of the ADC is 1.0pJ/bit, which is to date the best reported FoM for an RF ADC. An efficient algorithm for the tuning and calibration of the ΔΣ LC-based loop filter is also presented in this paper.