Title :
Processing and reliability of corner bonded CSPs
Author :
Toleno, Brian J. ; Schneide, Josef
Author_Institution :
Henkel Loctite, City of Industry, CA, USA
Abstract :
Chip scale packages (CSPs) are now widely used for many electronic applications including portable electronics, telecommunications, and automotive assemblies. Assemblers of these types of devices are looking for solutions that both decrease cost and increase reliability. Underfilling CSPs is known to increase the reliability of these devices. This process can be costly in materials, capital equipment, and process time. This paper presents an alternate solution, bonding the CSP at the corners and edges. This process is used to increase the reliability of CSP devices with respect to shock and vibration. The corner bonding material examined in this study can be dispensed prior to reflow along side the solder paste onto the substrate and cured during the reflow process. This paper will discuss the processing aspects and the reliability of the bonded device. Processing parameters to be discussed are the maximum displacement that allows self-alignment, the optimum placement of the corner bond material on packages with corner bumps will be presented, and dot diameter and heights. The second half of the paper discusses the reliability performance of the material in comparison with several traditional underfill materials. Reliability testing included performing drop testing and thermal cycling (-55°C to +125°C) on test vehicles. These studies were conducted are several sizes of components from a 35 mm×35 mm, 1.27 mm pitch, PBGA down to a 6 mm×8 mm, 0.75 mm microBGA.
Keywords :
ball grid arrays; bonding processes; chip scale packaging; curing; integrated circuit testing; reflow soldering; reliability; automotive assemblies; chip scale packages; corner bonding material; drop testing; microBGA; portable electronics; reflow process; reliability testing; solder paste; substrate; telecommunications; thermal cycling; underfill materials; Assembly; Automotive engineering; Bonding; Chip scale packaging; Conducting materials; Costs; Electric shock; Electronics packaging; Materials reliability; Testing;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. IEEE/CPMT/SEMI 28th International
Print_ISBN :
0-7803-7933-0
DOI :
10.1109/IEMT.2003.1225917