Title :
CMOS amplifier design with enhanced slew rate and power supply rejection
Author :
Lee, Bang W. ; Sheu, Bing J.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
The performance of several types of analog VLSI circuits is limited by the settling behavior and power supply rejection of CMOS amplifiers. Three novel techniques in MOS amplifier design, including nonsaturated input differential pair, improved cascode structure, and biasing circuitry, are described. A two-stage amplifier using these techniques has been fabricated in the MOSIS scalable 2-μm CMOS technology, and achieves 80-V/μs slew rate and 57-dB power-supply rejection ratio (PSRR) at 50 kHz with DC power dissipation of 1 mW
Keywords :
CMOS integrated circuits; VLSI; amplifiers; linear integrated circuits; 2 micron; 50 kHz; CMOS amplifier design; DC power dissipation; MOSIS scalable technology; biasing circuitry; cascode structure; nonsaturated input differential pair; power supply rejection; slew rate; two-stage amplifier; Analog-digital conversion; CMOS analog integrated circuits; CMOS technology; Differential amplifiers; Dynamic range; Operational amplifiers; Power amplifiers; Power supplies; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101884
