Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS

Random variations play a critical role in determining SRAM yield, by affecting both the bitcell and the read sense amplifiers (SA). In this work, a process control monitor for SRAM SA offset is proposed and implemented in 28nm LP CMOS technology. The monitor provides accurate measurement of SA offset from a large sample size and accounts for all proximity effects that may affect the SA offset. The all-digital design of the monitor makes it adequate for low voltage testing, high speed data collection, and ease of migration to newer technologies. Detailed measurement results are provided for two of the most commonly used sense amplifiers at different supply and temperature conditions. Statistical yield estimation using the measured sense amplifier offset shows good correlation with measured yield for a 512Kb SRAM. The monitor is a critical part of SRAM silicon yield validation, which is becoming of increasing importance with technology scaling, and the significant increase in random variations.