DocumentCode
1964571
Title
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS
Author
Reddy, Karthikeyan ; Dey, Siladitya ; Rao, Sachin ; Young, Brian ; Prabha, Praveen ; Hanumolu, Pavan Kumar
Author_Institution
Sch. of EECS, Oregon State Univ. Corvallis, Corvallis, OR, USA
fYear
2015
fDate
17-19 June 2015
Abstract
A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.
Keywords
CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; voltage-controlled oscillators; CMOS integrated circuit; bandwidth 50 MHz; continuous time delta-sigma ADC; dual phasefeedback; frequency feedback; power 54 mW; size 65 nm; wide bandwidth VCO; Bandwidth; CMOS integrated circuits; Computer architecture; Frequency modulation; Microprocessors; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-86348-502-0
Type
conf
DOI
10.1109/VLSIC.2015.7231278
Filename
7231278
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