A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias

We propose a new 2T mask ROM with dynamic column source bias control technique, which allows us to achieve both high-speed operation and low-power consumption. One can also overcome the inherent problem of the cross-talk noise between bitlines. The fabricated 128-kb ROM macro using 28-nm high-k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at 0.85 V, which is comparable with recent high-speed embedded SRAMs. Measured active power dissipation is 0.5× smaller than conventional 2T ROM. The standby leakage also can be reduced to a half of the conventional macros.