• DocumentCode
    1964805
  • Title

    A 450 MS/s 10-bit time-interleaved zero-crossing based ADC

  • Author

    Chu, J. ; Lee, H.-S.

  • Author_Institution
    Massachusetts Inst. of Technol., Cambridge, MA, USA
  • fYear
    2011
  • fDate
    19-21 Sept. 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A 450-MS/s 10-bit time-interleaved zero-crossing based pipelined ADC is described. The prototype ADC, fabricated in a 90-nm CMOS process, occupies 1.3 mm2. A reference pre-charging technique is applied to reduce the voltage ripples on the reference voltages. Gain, offset, and timing calibration is applied to achieve an 8.7 ENOB with a 211 MHz input signal and dissipates 34 mW from a 1.2V supply for a FOM of 182 fJ/step.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; pipeline processing; CMOS process; analog-digital converters; pipelined ADC; power 34 mW; reference precharging technique; reference voltage; size 90 nm; time interleaved zero crossing based ADC; voltage 1.2 V; voltage ripple reduction; Calibration; Capacitors; Clocks; Delay; Switches; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2011 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4577-0222-8
  • Type

    conf

  • DOI
    10.1109/CICC.2011.6055327
  • Filename
    6055327
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1964805