DocumentCode
1965183
Title
An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS
Author
Park, Youngmin ; Wentzloff, David D.
Author_Institution
Univ. of Michigan, Ann Arbor, MI, USA
fYear
2011
fDate
19-21 Sept. 2011
Firstpage
1
Lastpage
4
Abstract
This paper presents an all-digital PLL (ADPLL) in which all functional blocks have been synthesized from standard digital cells and automatically placed and routed (P&R). A calibration scheme is proposed to account for the systematic mismatch resulting from P&R. The ADPLL is fabricated in 65nm CMOS and occupies 0.042mm2. The period jitter is 3.2psrms (36pspp) at 2.5GHz, and the power consumption is 9.1mW to 14.6mW over a 1.5 to 2.7GHz frequency range.
Keywords
CMOS digital integrated circuits; calibration; digital phase locked loops; jitter; ADPLL; CMOS process; P&R; all-digital PLL; calibration scheme; digital standard cell library; frequency 1.5 GHz to 2.7 GHz; functional block; period jitter; placed and routed; power 9.1 mW to 14.6 mW; power consumption; size 65 nm; systematic mismatch; time 3.2 ps; Buffer storage; CMOS integrated circuits; Calibration; Computer architecture; Frequency control; Frequency measurement; Systematics;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4577-0222-8
Type
conf
DOI
10.1109/CICC.2011.6055347
Filename
6055347
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