• DocumentCode
    1965205
  • Title

    An open-loop 10GHz 8-phase clock generator in 65nm CMOS

  • Author

    Yang, Xiaochen ; Liu, Jin

  • Author_Institution
    Univ. of Texas at Dallas, Richardson, TX, USA
  • fYear
    2011
  • fDate
    19-21 Sept. 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    An open-loop 10GHz 8-phase clock generator is presented. The open-loop architecture is composed of delay units and phase interpolators with built-in phase compensation for delay time variation of delay units. A delay unit design with level-shifted active inductor load enables the circuit to achieve 10GHz speed with 0.19mW/GHz/phase power efficiency in 65nm CMOS. The 8-phase clock generator can operate from 8GHz to 12GHz with good phase accuracy and occupies 1500μm2 active die area.
  • Keywords
    CMOS digital integrated circuits; clocks; field effect MMIC; phase locked loops; CMOS technology; built-in phase compensation; delay time variation; delay unit design; frequency 8 GHz to 12 GHz; level-shifted active inductor load; open-loop 8-phase clock generator; open-loop architecture; phase interpolators; power 0.19 mW; size 65 nm; Active inductors; Clocks; Delay; Delay lines; Generators; Jitter; Semiconductor device measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2011 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4577-0222-8
  • Type

    conf

  • DOI
    10.1109/CICC.2011.6055348
  • Filename
    6055348
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1965205