Title :
A 3.2 GOPS multiprocessor DSP for communication applications
Author :
Williams, J. ; Singh, K.J. ; Nicol, C. ; Sackinger, E. ; Daubert, S. ; Micca, E. ; Moturi, M. ; Knobloch, J. ; Brinthaupt, D. ; Ackland, B.
Author_Institution :
Lucent Technol., Bell Labs., Holmdel, NJ, USA
Abstract :
This programmable DSP is the first implementation of the scaleable-bus-based platform, Daytona for communication infrastructure equipment and broadband access terminals. An aggressive memory hierarchy minimizes bus traffic and meets the performance requirements for large multi-channel signal processing applications with the smallest possible memory footprint. The chip was implemented with full custom memories with 0.35 /spl mu/m features and the remaining logic is implemented with standard cells. The 207 mm/sup 2/ 0.25 /spl mu/m CMOS chip achieves 100 MHz and dissipates 4 W at 3.3 V.
Keywords :
CMOS digital integrated circuits; digital signal processing chips; pipeline processing; programmable circuits; reduced instruction set computing; 0.25 mum; 3.2 GOPS multiprocessor DSP; 3.3 V; 32 bit; 4 W; CMOS chip; Daytona for communication infrastructure equipment; RISC processor; aggressive memory hierarchy; broadband access terminals; communication applications; full custom memories; large multi-channel signal processing applications; memory footprint; power dissipation; programmable DSP; scaleable-bus-based platform; standard cells; Buffer storage; Communication system traffic control; Coprocessors; Delay; Digital signal processing; Memory management; Pipelines; Protocols; Reduced instruction set computing; Signal processing;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839695
