An Event-Assisted Sequencer to Accelerate Matrix Algorithms

This paper presents a sequencer that accelerates matrix algorithms arising naturally in many multimedia and signal processing applications. The accelerator has been designed to carry out data management tasks common to these algorithms. A novel event-based parameter update mechanism allows production of continuously varying patterns to access triangular, banded and other irregular matrix structures. It has been verified that the accelerator significantly reduces the workload of the attached CPU for a wide range of algorithms. The accelerator has been implemented on a Virtex-5 FPGA platform where it required 1856 slices and achieved a post place-and-route speed of 64 MHz.