A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI

Author

Sanduleanu, M.A.T. ; Reynolds, S. ; Plouchart, J.O.

Author_Institution

IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

4

Abstract

A 4GS/s sampling system achieved 8.45-ENOB linearity with 5.7fJ/conversion energy efficiency at 1V power supply and its gain can be adjusted in a digital manner. The measured IIP3 and IIP2 are 17.7dBm and 40dBm respectively. The ENOB of the sampler shows no degradation up to Nyquist frequency. An integrated phase rotator allows digital clock delay and duty cycle adjustment with sub-picosecond resolution. The sampling system tracks and settles in 1/4UI (62.5ps). Realized in a 45nm SOI CMOS the active area of the sampler is only 0.2×0.2mm².

Keywords

CMOS digital integrated circuits; analogue-digital conversion; clocks; delays; silicon-on-insulator; CMOS SOI; ENOB linearity; IIP2 measurement; IIP3 measurement; Nyquist frequency; conversion energy efficiency; digital assisted sampling system; digital clock delay; duty cycle adjustment; integrated phase rotator; size 45 nm; subpicosecond resolution; time-interleaved A/D architecture; Bandwidth; CMOS integrated circuits; Clocks; Delay; Distortion measurement; Linearity; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055383

Filename

6055383