Title :
Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits
Author :
Ubar, Raimund ; Devadze, Sergei ; Raik, Jaan ; Jutman, Artur
Author_Institution :
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
Abstract :
In this paper, a new very fast fault simulation method for extended class of faults is proposed. The method is based on a two-phase procedure. In the first phase, a novel parallel exact critical path fault tracing is used to determine all the "active" nodes with detectable stuck-at faults. In the second phase of the procedure, reasoning is carried out to determine the detectable physical defects based on the information about the "active" nodes and the current (or previous) logic state of the network.
Keywords :
fault simulation; logic testing; active nodes; extended fault classes; fault detection; fault simulation; logic state; parallel exact critical path fault tracing; scan path circuits; stuck-at faults; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Computer simulation; Electrical fault detection; Failure analysis; Fault detection; Fault diagnosis; digital circuits; extended fault classes; fault analysis; fault simulation; parallel exact critical path tracing;
Conference_Titel :
Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on
Conference_Location :
Ho Chi Minh City
Print_ISBN :
978-0-7695-3978-2
Electronic_ISBN :
978-1-4244-6026-7
DOI :
10.1109/DELTA.2010.32
