An efficient test-data compaction for low power VLSI testing

This paper presents an input test data compaction and scan power reduction technique. We present new design for testability (DFT) method to hold values when some of test data in test cubes are not need to be changed. In our implementation, we present new algorithm called 2-D compaction to compact test cubes as less as possible and fill unspecified bits with specified value when necessary. Experimental results show a high compaction ratio improvement and amount of test data bits is close to compression effect. Itpsilas suggested that our method is promising for greatly reduce peak power and heat dissipation.