Title :
Spice simulation of 0.18 /spl mu/m CMOS ring oscillators using physical models for capacitance and series resistance
Author :
Biesemans, S. ; Kubicek, S. ; De Meyer, K.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
We present a case study in which ring oscillators, with 0.18 /spl mu/m channel length, are measured and compared with Spice simulations. It is found that good quantitative results can be obtained for several process splits. Special care is taken to include a physical model for the parasitic series resistance R/sub s/(V/sub gs/) and to model correctly the parasitic capacitances obtained from the mask layout.
Keywords :
SPICE; 0.18 micron; CMOS ring oscillators; Spice simulation; channel length; mask layout; parasitic capacitances; parasitic series resistance; physical models; process splits; Application specific processors; Capacitance measurement; Electrical resistance measurement; Implants; Integrated circuit interconnections; Length measurement; MOS devices; Parasitic capacitance; SPICE; Semiconductor device modeling;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.650278
