A 720 /spl mu/W 50 MOPs 1V DSP for a hearing aid chip set

This paper presents the flow and techniques used to design a digital signal processor chip used in a new hearing aid implementing multi-band compression, noise cancellation, pattern recognition and adaptive filtering. The pad-limited 20 mm/sup 2/ chip contains 1.3 M transistors and operates at 2.5 MHz at 0.9 V (1.05 V worst case). The DSP consumes 720 /spl mu/W under the nominal 1.2 V supply and performs 50 M 22 b operations per second. The DSP achieves 0.015 mW/MOP/s, 6/spl times/ better than prior results in this field. The chip uses a conventional 0.25 /spl mu/m process with normal threshold voltages.