A 1.25 Gb/s CMOS receiver core with plesiochronous clocking capability for asynchronous burst data acquisition

To realize GB/s data acquisition while suppressing EMI problems, multiport (parallel) optical interconnection is desired. In multiport optical interconnections, a CMOS receiver core in the receiver (which receives serial data from PD array and amplifier) must have (i) >1 Gb/s data acquisition capability with clock recovery for reception of long data streams, (ii) asynchronous burst data acquisition capability to avoid complicated data modulation, (iii) low power dissipation required for multiport receiver LSIs. The authors present a prototype chip, which is fabricated in a 0.25 /spl mu/m CMOS process, to implement these requirements.