• DocumentCode
    1967643
  • Title

    Accurate analysis of multistage interconnection networks using finite output-buffered switching elements

  • Author

    Zhou, Bin ; Atiquzzaman, M.

  • Author_Institution
    Dept. of Comput. Sci., La Trobe Univ., Melbourne, Vic., Australia
  • Volume
    2
  • fYear
    1995
  • fDate
    19-21 Apr 1995
  • Firstpage
    838
  • Abstract
    Many of the existing analytical models for output buffered switching elements (SE) assume uniform traffic and infinite buffers at each output port of an SE. Moreover, because of simplifying assumptions, the results are not accurate. It is important to develop an accurate analytical model to tailor the design of the network parameters and optimize the network performance by proper dimensioning of the buffers. The objective of this paper is to develop an accurate model for the performance of MINs using finite output buffered SEs, and operating in the presence of nonuniform traffic patterns. It is shown that the proposed analytical model is much accurate than existing models
  • Keywords
    buffer storage; multistage interconnection networks; performance evaluation; finite output-buffered switching elements; multistage interconnection networks; network parameters; network performance; nonuniform traffic patterns; Analytical models; Asynchronous transfer mode; Australia; B-ISDN; Clocks; Large-scale systems; Multiprocessing systems; Multiprocessor interconnection networks; Telecommunication traffic; Traffic control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP., IEEE First International Conference on
  • Conference_Location
    Brisbane, Qld.
  • Print_ISBN
    0-7803-2018-2
  • Type

    conf

  • DOI
    10.1109/ICAPP.1995.472274
  • Filename
    472274