Leakage Reduction of Power-Gating Sequential Circuits Based on Complementary Pass-Transistor Adiabatic Logic Circuits

Leakage dissipation is more and more dominant. Limiting leakage power consumption becomes an important factor in IC designs. This paper presents a reduction technique of leakage consumption for adiabatic sequential circuits based on two-phase CPAL (complementary pass-transistor adiabatic logic) using power-gating scheme. A practical sequential circuit with a mode-5×5×5 counter using two-phase CPAL is demonstrated. All circuits are verified using HSPICE, and BSIM4 model is adopted to reflect the characteristics of the leakage currents. With 45 nm and 90 nm CMOS process, simulation results show that the leakage losses of the adiabatic sequential circuits with the power-gating scheme are greatly reduced compared with static CMOS one.