A 550 Mb/s GMR read/write amplifier using 0.5 /spl mu/m 5 V CMOS process

Author

Lamb, S. ; Cheng, L. ; Young, D.

Author_Institution

Marvell Semicond. Inc., Sunnyvale, CA, USA

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

358

Lastpage

359

Abstract

The read/write amplifier is one of the key components in hard disk drive (HDD) design. Traditionally, BiCMOS technology has been the main stream process for preamplifier design. However, with recent advances in CMOS processing, CMOS implementation is more cost-effective and more suitable for chip on suspension due to smaller die size, and is high-performance in terms of noise, gain accuracy, channel-to-channel matching, bandwidth, PSSR and write-current rise/fall time. The 8-channel read/write amplifier is fabricated in a 0.5 /spl mu/m 5 V double-poly, double-metal CMOS process. Coupled with an advanced write head, this high performance read/write amplifier supports >550 Mb/s data rate.

Keywords

CMOS integrated circuits; disc drives; mixed analogue-digital integrated circuits; preamplifiers; 0.5 micron; 5 V; 550 Mbit/s; 8-channel read/write amplifier; GMR read/write amplifier; double-poly double-metal CMOS proces; hard disk drive; preamplifier design; submicron CMOS process; write driver; Bandwidth; CMOS process; Circuit noise; Driver circuits; Low-noise amplifiers; Noise level; Parasitic capacitance; Semiconductor optical amplifiers; Temperature sensors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839815

Filename

839815