A 56.8 GB/s 0.18 /spl mu/m embedded DRAM macro with dual port sense amplifier for 3D graphics controller

Author

Yamazaki, A. ; Fujino, T. ; Inoue, K. ; Hayashi, I. ; Noda, H. ; Watanabe, N. ; Morishita, F. ; Ootani, J. ; Kobayashi, M. ; Dosaka, K. ; Morooka, Y. ; Shimano, H. ; Soeda, S. ; Hachisuka, A. ; Okumura, Y. ; Arimoto, K. ; Wake, S. ; Ozaki, H.

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

394

Lastpage

395

Abstract

Advanced 3D graphics (3DG) technology will be used in console game machines, and it is desired to develop a rendering controller chip which can handle real time 3D animation with true colors. Embedded DRAM (eDRAM) technology attracts attention of the 3DG systems, because only eDRAM can satisfy the required data rate. Four or more pipelines, 200 MHz pipeline operating frequency, and 64 b per pixel are required. With this configuration, the required data rate is 39.4 GB/s, assuming the total penalty of 35% for page miss and video refresh. Furthermore, a 120 Mb frame buffer is required for a 1280/spl times/1024-pixels screen. This 0.18 /spl mu/m 32 Mb eDRAM macro satisfies these requirements.

Keywords

DRAM chips; cellular arrays; computer animation; computer graphic equipment; embedded systems; operational amplifiers; redundancy; rendering (computer graphics); 0.18 micron; 3D graphics controller; 56.8 Gbit/s; console game machines; dual port sense amplifier; embedded DRAM macro; pipelines; real time 3D animation; rendering controller chip; true colors; Animation; Circuit testing; Delay; Energy consumption; Frequency; Graphics; Multichip modules; Pipelines; Random access memory; Rendering (computer graphics);

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839830

Filename

839830