DocumentCode
1968339
Title
A 0.18 /spl mu/m 256 Mb DDR-SDRAM with low-cost post-mold-tuning method for DLL replica
Author
Kuge, S. ; Kato, T. ; Furutani, K. ; Kikuda, S. ; Mitsui, K. ; Hamamoto, T. ; Setogawa, J. ; Hamade, K. ; Komiya, Y. ; Kawasaki, S. ; Kono, T. ; Amano, T. ; Kubo, T. ; Haraguchi, M. ; Kawaguchi, Z. ; Nakaoka, Y. ; Akiyama, M. ; Konishi, Y. ; Ozaki, H.
Author_Institution
ULSI Dev. Centre, Mitsubishi Electr. Corp., Itami, Japan
fYear
2000
fDate
9-9 Feb. 2000
Firstpage
402
Lastpage
403
Abstract
A delay-locked loop (DLL) must have a large delay line to work over a wide range of frequency. This makes the layout area larger. A hierarchy delay line solves this problem. But coarse and fine delay changing at the same time causes jitter. This DLL and voltage down converter (VDC) avoids the jitter problem.
Keywords
DRAM chips; delay lock loops; memory architecture; phase detectors; timing jitter; 0.18 micron; 256 Mbit; DLL replica; double-data-rate-SDRAM; hierarchy delay line; jitter problem; low-cost post-mold-tuning method; phase detector; replica tuning; voltage down converter; Circuit optimization; Circuit testing; Clocks; Counting circuits; Delay lines; Fuses; Jitter; Laser tuning; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-5853-8
Type
conf
DOI
10.1109/ISSCC.2000.839834
Filename
839834
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