Antifuse EPROM circuit for field programmable DRAM

A 3 V EPROM circuit is implemented in an existing 0.22 /spl mu/m DRAM process with an antifuse based on destructive breakdown of the highly-reliable 6.5 nm oxide-nitride-oxide (ONO) storage capacitor dielectric. Using an internal high-voltage charge pump, this antifuse EPROM is programmed without external high-voltage power supplies which facilitates full pin compatibility with existing SDRAM specifications. This antifuse EPROM circuit enables field programmable DRAM functionality such as post-package memory repair, output impedance matching for system memory module calibration, user programmable memory bank architectures, data encryption, and product serial numbers. While laser programmable polysilicon fuses are used extensively to provide nonvolatile memory for repair of defective DRAM cells, they are limited to programming at wafer level and before packaging. Previous implementations of antifuse EPROM utilized external high-voltage supplies for wafer level programming only due to the incompatibility of high voltage power supplies with existing DRAM pin configurations.